1. Field
Embodiments of the invention relate generally to a nonvolatile semiconductor memory device that can electrically rewrite data and a method for manufacturing the same.
2. Background Art
Conventionally, semiconductor memory devices, such as flash memories, have been fabricated by two-dimensionally integrating memory cells on the surface of a silicon substrate. In this type of semiconductor memory device, increase in the packaging density of memory cells is required to reduce cost per bit and increase memory capacity. However, recently, such increase in the packaging density has been difficult in terms of cost and technology.
Methods of stacking memory cells for three-dimensional integration are known as techniques for breaking through the limit of packaging density. However, in the method of simply stacking and patterning layer by layer, increase in the number of stacked layers results in increasing the number of processes and increasing cost. In particular, increase in the number of lithography processes for patterning the structure of a transistor is a primary factor in increased cost. Thus, reduction in chip area per bit by layer stacking is not so effective in reducing cost per bit as downscaling in the chip surface, and is not suitable as a method for increasing memory capacity.
In consideration of such problems, the inventors, etc. proposed a simultaneously patterned three-dimensional stacked memory (for example, refer to JP-A 2007-266143 (Kokai)). In this technique, a stacked body is formed on a silicon substrate by alternately stacking electrode films and insulating films and subsequently making through-holes in the stacked body by collective patterning. A charge storage layer is formed on the side surface of the through-hole, and the through-hole is filled with a silicon pillar. Thus, a memory transistor is formed at an intersection between each electrode films and the silicon pillar.
In this simultaneously patterned three-dimensional stacked memory, information can be stored by controlling the potential of each electrode film and each silicon pillar to transfer charge between the silicon pillar and the charge storage layer. In this technique, through holes are formed by simultaneously patterning the stacked body. Hence, increase in the number of stacked electrode films does not result in increasing the number of lithography processes, and cost increase can be suppressed.
In such a simultaneously patterned three-dimensional stacked memory, a cell array section having three-dimensionally arranged memory transistors and a peripheral circuit section for driving the cell array section are provided and the peripheral circuit section applies a control potential to the cell array section through an interconnect. Moreover, when such simultaneously patterned three-dimensional stacked memory is fabricated, it is preferred that an electrode in a lower portion of the cell array section is formed simultaneously with the gate electrode of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) provided in the peripheral circuit section for simplification of manufacturing process. In this case, the gate electrode of the MOSFET is typically formed of a semiconductor material doped with impurities, and thus it follows that the electrode in the lower portion of the cell array section is also formed of the semiconductor material doped with impurities. This disadvantageously results in increasing the resistance of the electrode.